[ActiveSupport PAR]
; Global primary clocks
GLOBAL_PRIMARY_USED = 2;
; Global primary clock #0
GLOBAL_PRIMARY_0_SIGNALNAME = clk_c;
GLOBAL_PRIMARY_0_DRIVERTYPE = PIO;
GLOBAL_PRIMARY_0_LOADNUM = 865;
; Global primary clock #1
GLOBAL_PRIMARY_1_SIGNALNAME = time_generator_inst/clk_5hz;
GLOBAL_PRIMARY_1_DRIVERTYPE = SLICE;
GLOBAL_PRIMARY_1_LOADNUM = 15;
; # of global secondary clocks
GLOBAL_SECONDARY_USED = 8;
; Global secondary clock #0
GLOBAL_SECONDARY_0_SIGNALNAME = clk_c_enable_659;
GLOBAL_SECONDARY_0_DRIVERTYPE = SLICE;
GLOBAL_SECONDARY_0_LOADNUM = 306;
GLOBAL_SECONDARY_0_SIGTYPE = CE;
; Global secondary clock #1
GLOBAL_SECONDARY_1_SIGNALNAME = piano_out_I_0/clk_c_enable_1414;
GLOBAL_SECONDARY_1_DRIVERTYPE = SLICE;
GLOBAL_SECONDARY_1_LOADNUM = 26;
GLOBAL_SECONDARY_1_SIGTYPE = CE;
; Global secondary clock #2
GLOBAL_SECONDARY_2_SIGNALNAME = uart_top_inst/n26803;
GLOBAL_SECONDARY_2_DRIVERTYPE = SLICE;
GLOBAL_SECONDARY_2_LOADNUM = 26;
GLOBAL_SECONDARY_2_SIGTYPE = RST;
; Global secondary clock #3
GLOBAL_SECONDARY_3_SIGNALNAME = uart_top_inst/n26802;
GLOBAL_SECONDARY_3_DRIVERTYPE = SLICE;
GLOBAL_SECONDARY_3_LOADNUM = 26;
GLOBAL_SECONDARY_3_SIGTYPE = RST;
; Global secondary clock #4
GLOBAL_SECONDARY_4_SIGNALNAME = uart_top_inst/n26798;
GLOBAL_SECONDARY_4_DRIVERTYPE = SLICE;
GLOBAL_SECONDARY_4_LOADNUM = 26;
GLOBAL_SECONDARY_4_SIGTYPE = RST;
; Global secondary clock #5
GLOBAL_SECONDARY_5_SIGNALNAME = uart_top_inst/n26804;
GLOBAL_SECONDARY_5_DRIVERTYPE = SLICE;
GLOBAL_SECONDARY_5_LOADNUM = 26;
GLOBAL_SECONDARY_5_SIGTYPE = RST;
; Global secondary clock #6
GLOBAL_SECONDARY_6_SIGNALNAME = uart_top_inst/n26794;
GLOBAL_SECONDARY_6_DRIVERTYPE = SLICE;
GLOBAL_SECONDARY_6_LOADNUM = 26;
GLOBAL_SECONDARY_6_SIGTYPE = RST;
; Global secondary clock #7
GLOBAL_SECONDARY_7_SIGNALNAME = uart_top_inst/n26797;
GLOBAL_SECONDARY_7_DRIVERTYPE = SLICE;
GLOBAL_SECONDARY_7_LOADNUM = 26;
GLOBAL_SECONDARY_7_SIGTYPE = RST;
; I/O Bank 0 Usage
BANK_0_USED = 2;
BANK_0_AVAIL = 26;
BANK_0_VCCIO = 3.3V;
BANK_0_VREF1 = NA;
; I/O Bank 1 Usage
BANK_1_USED = 11;
BANK_1_AVAIL = 26;
BANK_1_VCCIO = 3.3V;
BANK_1_VREF1 = NA;
; I/O Bank 2 Usage
BANK_2_USED = 13;
BANK_2_AVAIL = 28;
BANK_2_VCCIO = 3.3V;
BANK_2_VREF1 = NA;
; I/O Bank 3 Usage
BANK_3_USED = 1;
BANK_3_AVAIL = 7;
BANK_3_VCCIO = 3.3V;
BANK_3_VREF1 = NA;
; I/O Bank 4 Usage
BANK_4_USED = 0;
BANK_4_AVAIL = 8;
BANK_4_VCCIO = NA;
BANK_4_VREF1 = NA;
; I/O Bank 5 Usage
BANK_5_USED = 1;
BANK_5_AVAIL = 10;
BANK_5_VCCIO = 3.3V;
BANK_5_VREF1 = NA;
